UC知道VHDL编译错误
来源：百度知道 编辑：UC知道 时间：2024/05/24 23:04:17
这是我的VHDL源程序：
--
-- file: p2r_CordicPipe.vhd
-- author: Richard Herveille
-- rev. 1.0 initial release
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity p2r_CordicPipe is
generic(
WIDTH : natural := 16;
PIPEID : natural := 1
);
port(
clk : in std_logic;
ena : in std_logic;
Xi : in signed(WIDTH -1 downto 0);
Yi : in signed(WIDTH -1 downto 0);
Zi : in signed(19 downto 0);
Xo : out signed(WIDTH -1 downto 0);
Yo : out signed(WIDTH -1 downto 0);
Zo : out signed(19 downto 0)
);
end entity p2r_CordicPipe;
architecture dataflow of p2r_CordicPipe is
function CATAN(n :natural) return integer is
variable result :integer;
begin
case n is
when 0 => result := 16#020000#;
when 1 => result := 16#012E40#;
when 2 => result := 16#0
--
-- file: p2r_CordicPipe.vhd
-- author: Richard Herveille
-- rev. 1.0 initial release
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity p2r_CordicPipe is
generic(
WIDTH : natural := 16;
PIPEID : natural := 1
);
port(
clk : in std_logic;
ena : in std_logic;
Xi : in signed(WIDTH -1 downto 0);
Yi : in signed(WIDTH -1 downto 0);
Zi : in signed(19 downto 0);
Xo : out signed(WIDTH -1 downto 0);
Yo : out signed(WIDTH -1 downto 0);
Zo : out signed(19 downto 0)
);
end entity p2r_CordicPipe;
architecture dataflow of p2r_CordicPipe is
function CATAN(n :natural) return integer is
variable result :integer;
begin
case n is
when 0 => result := 16#020000#;
when 1 => result := 16#012E40#;
when 2 => result := 16#0
我在QuartusII 里编译了你的程序，报错：
Error (10500): VHDL syntax error at p2r_CordicPipe.vhd.vhd(58) near text "compatibility"; expecting "begin", or a declaration statement
“compatibility with Xilinx WebPack ”这一行，你用的Xilinx器件，是不是应该用 ModleSim （参考http://www.edacn.net/bbs/thread-68737-1-1.html），而你用的Altera公司的MAX Plus II
楼主在：compatibility with Xilinx WebPack
这句前面加两个减号“--”注释掉就对了。那句不是VHDL语句。
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不得不补充一句，tangbin76229不要误导别人。p2r_CordicPipe.vhd在OpenCore上的源代码我也看过了，那句纯粹就是注释。
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回复楼主，我用的是ModelSim6.2，编译通过了。。。