一个关于VHDL的问题

同学，首先，你少了一句：architecture XXXX of ym is 把这句加上；当然，后面还少了个begin
所以修改后的程序为：
===============================
library ieee;
use ieee.std_logic_1164.all;

entity ym is
port(a:in std_logic_vector(6 downto 0);
s:out std_logic_vector(2 downto 0);
b:out std_logic_vector(3 downto 0);
c:out std_logic_vector(2 downto 0));
end ;
architecture one of ym is
begin
process(a)
variable ss:std_logic_vector(2 downto 0);
variable bb:std_logic_vector(6 downto 0);
begin
ss(2):=a(6) xor a(5) xor a(4) xor a(2);
b(1)<=a(3) xor a(2) xor a(0);
b(0)<=a(3) xor a(1) xor a(0);
ss(1):=a(6) xor a(5) xor a(3) xor a(1);
ss(0):=a(6) xor a(4) xor a(3) xor a(0);
if ss> "000" then
case ss is
when "001" =>bb(0):= not bb(0);c<="000";
when "010" =>bb(1):= not bb(1);c<="001";
when "100" =>