eda 用case 语句怎么编写异或门程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1146.ALL;
ENTITY XXX IS
PORT(a,b:IN STD_LOGIC;
y:OUT STD_LOGIC);
END ENTITY XXX;
ARCHITECTURE aaa OF XXX IS
SIGANL S:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
S<=a & b;
PROCESS(S)
BEGIN
CASE S IS
WHEN "00"=>y<='0';
WHEN "01"=>y<='1';
WHEN "10"=>y<='1';
WHEN "11"=>y<='0';
WHEN OTHERS=>NULL;
END CASE;
END PROCESS;
END ARCHITECTURE aaa;

library ieee;
use ieee.std_logic_1164.all;
entity xor_1 is
port (a,b:in std_logic
xx:out std_logic)
end;
architecture ar of xor_1 is
signal a_b:std_logic_vector(1 downto 0)
begin
process(a,b)
begin
a_b<=a&b;
case a_b is
when "00"=>xx<=0;
when "01"=>xx&