用VHDL设计4选一数据选择器，然后用生成语句设计双4选1数据选择器

以前做过来着，但是记不全。楼主把四选一机制，和输入输出变量要求补充一下吧。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux4 is
port(d0,d1,d2,d3 :in std_logic;
a0,a1 :in std_logic;
q :out std_logic);
end mux4;
architecture behavioral of mux4 is
signal sel :integer;
begin
with sel select
q <= d0 after 10ns when 0, d1 after 10ns when 1, d2 after 10ns when 2,
d3 after 10ns when 3, ‘x’ after 10ns when other;
sel <= 0 when a0 =‘0’ and a1 =‘0’ else 1 when a0 =‘1’ and a1 =‘0’ else
2 when a0 =‘0’ and a1 =‘1’ else 3 when a0 =‘1’ and a1 =‘1’ else 4;
end behavioral