UC知道关于cpld的问题，麻烦各位大虾看看！
来源：百度知道 编辑：UC知道 时间：2024/06/07 01:31:39
准备用CPLD编一个频率计，但fit总是过不了，显示如下：
Mapping a total of 62 equations into 6 function blocks...............................................ERROR:Cpld:892 - Cannot place signal XLXI_1/cnt5<1>. Consider reducing the
collapsing input limit or the product term limit to prevent the fitter from
creating high input and/or high product term functions.
See the fitter report for details.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.
ERROR: Fit failed
Reason:
Process "Fit" did not complete.
我用的是xc95108
麻烦各位帮忙看看，谢谢！
实验室只提供了这一种芯片，可不可以给出其它解决办法或是优化程序的建议？
Mapping a total of 62 equations into 6 function blocks...............................................ERROR:Cpld:892 - Cannot place signal XLXI_1/cnt5<1>. Consider reducing the
collapsing input limit or the product term limit to prevent the fitter from
creating high input and/or high product term functions.
See the fitter report for details.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.
ERROR: Fit failed
Reason:
Process "Fit" did not complete.
我用的是xc95108
麻烦各位帮忙看看，谢谢！
实验室只提供了这一种芯片，可不可以给出其它解决办法或是优化程序的建议？
应该是设置不对，导致无法适配到选定的器件。检查下选用器件及其选项部分。
其实这种情况在使用Quartus II来仿真时是很常见的！
“Cannot fit the design into any of the specified devices with the selected implementation options.”意思是你所选择的那款CPLD\FPGA不能实现你设计中的要求。
解决方法很简单：只需要选用另外一款能实现你设计要求的一款CPLD\FPGA即可！