施密特触发器能用verilog写吗？

可以
施密特触发器有2个阀指，来决定是 1 或是0
输入是模拟信号

module schmit(
data_in;
high_level;
low_level;
out,
clk,
reset_n
);
input data_in; //analog input
input high_level;//analog input, set the level of high signal
input low_level;//analog input, set the level of low signal
output out;//digital output
input clk;
input reset_n;

always@(posedge clk or negedge reset_n)begin:schmit
if(!reset_n) out <= 1'b0;
else
out <= (data_in >high_level)? 1'b1 : (data_in <low_level)? 1'b0:out;
end

可以
施密特触发器有2个阀指，来决定是 1 或是0
输入是模拟信号

module schmit(
data_in;
high_level;
low_level;
out,
clk,
reset_n
);
input data_in; //analog input
input high_level;//analog input, set the level of high signal
input low_level;//analog input, set the level of low signal
output out;//digital output
input clk;<