十进制计数器 vhdl
来源:百度知道 编辑:UC知道 时间:2024/06/15 06:31:02
LIBRARY IEEE;TY CNT10 IS &n
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 ISEE.STD_LOGIC_1164.AL
PORT (CLK,RST,EN : IN STD_LOGIC;
CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT : OUT STD_LOGIC ); L; USE IEEE.STD_LOGI
END CNT10;
ARCHITECTURE behav OF CNT10 IS
BEGINC_UNSIGNED.ALL; ENTI
PROCESS(CLK, RST, EN)
VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGINLIBRARY IEEE; USE IE
IF RST = '1' THEN CQI := (OTHERS =>'0') ; --计数
ELSIF CLK'EVENT AND CLK='1' THEN L; USE IEEE.STD_LOGI
IF EN = '1' THEN
IF CQI < 9 THEN CQI := CQI + 1; --允许计数,
TY CNT10 IS &n
ELSE CQI := (OTHERS =>'0')