UC知道PROTEL 99 SE中，进行DRC检查出现如下错误是什么原因
来源：百度知道 编辑：UC知道 时间：2024/05/20 21:02:20
如何改正
Processing Rule : Width Constraint (Min=8mil) (Max=8mil) (Prefered=10mil) (On the board )
Violation Track (3280mil,5160mil)(3328mil,5208mil) TopLayer Actual Width = 10mil
Violation Track (3328mil,5208mil)(3328mil,5392mil) TopLayer Actual Width = 10mil
Violation Track (3312mil,5408mil)(3328mil,5392mil) TopLayer Actual Width = 10mil
Violation Track (2948mil,5408mil)(3312mil,5408mil) TopLayer Actual Width = 10mil
Violation Track (2900mil,5360mil)(2948mil,5408mil) TopLayer Actual Width = 10mil
Violation Track (2240mil,5360mil)(2288mil,5408mil) TopLayer Actual Width = 10mil
Violation Track (2288mil,5408mil)(2852mil,5408mil) TopLayer Actual Width = 10mil
Violation Track (2852mil,5408mil)(2900mil,5360mil) TopLayer Actual Width = 10mil
Violation Track (4104mil,5104mil)(4200mil,5200mil) TopLayer Actual Width = 10mil
Processing Rule : Width Constraint (Min=8mil) (Max=8mil) (Prefered=10mil) (On the board )
Violation Track (3280mil,5160mil)(3328mil,5208mil) TopLayer Actual Width = 10mil
Violation Track (3328mil,5208mil)(3328mil,5392mil) TopLayer Actual Width = 10mil
Violation Track (3312mil,5408mil)(3328mil,5392mil) TopLayer Actual Width = 10mil
Violation Track (2948mil,5408mil)(3312mil,5408mil) TopLayer Actual Width = 10mil
Violation Track (2900mil,5360mil)(2948mil,5408mil) TopLayer Actual Width = 10mil
Violation Track (2240mil,5360mil)(2288mil,5408mil) TopLayer Actual Width = 10mil
Violation Track (2288mil,5408mil)(2852mil,5408mil) TopLayer Actual Width = 10mil
Violation Track (2852mil,5408mil)(2900mil,5360mil) TopLayer Actual Width = 10mil
Violation Track (4104mil,5104mil)(4200mil,5200mil) TopLayer Actual Width = 10mil
你在design下面的ruls里面，把Width Constraint 改成(Min=10mil) (Max=10mil) (Prefered=10mil).因为你把线宽最大只设置了8mil，而prefered大于8mil，所以你检查的时候会出错
我一般做完PCB只检查开路短路 别的不检查的 管他出什么错呢