UC知道电气论文翻译
来源：百度知道 编辑：UC知道 时间：2024/06/20 06:20:41
1. Variation-Tolerant Design
With the increase of process parameter variations in CMOS technologies due to the processing and masking limitations, power and performance variations become major concerns of circuit designers. Techniques such as the use of forward/reverse body bias and voltage scaling are commonly used to bring down the delay and power consumption specifications in the acceptable range. Variation-aware circuit sizing is another technique used at the design stage to have a more variation-tolerant circuit.
The key goal of this research is to provide techniques for designing more variation-tolerant circuits. We propose to attack the problem both at the design stage and at the post-fabrication stage. The latter requires the feasibility of having ways of specification tuning and a fast and efficient framework that makes the post-silicon tuning attractive. The summary of the proposed techniques is as follows:
With the increase of process parameter variations in CMOS technologies due to the processing and masking limitations, power and performance variations become major concerns of circuit designers. Techniques such as the use of forward/reverse body bias and voltage scaling are commonly used to bring down the delay and power consumption specifications in the acceptable range. Variation-aware circuit sizing is another technique used at the design stage to have a more variation-tolerant circuit.
The key goal of this research is to provide techniques for designing more variation-tolerant circuits. We propose to attack the problem both at the design stage and at the post-fabrication stage. The latter requires the feasibility of having ways of specification tuning and a fast and efficient framework that makes the post-silicon tuning attractive. The summary of the proposed techniques is as follows:
译文如下：
1。Variation-Tolerant设计,
与不断增长的过程中由于CMOS工艺参数的变化对加工和掩蔽的局限性,力量和性能差异的主要问题成为电路设计者。技术,如使用正转/反转电压偏置,身体常用来降低延迟和功耗规格在合格范围。Variation-aware浆纱是另一个技术的应用电路设计阶段,有更多的variation-tolerant电路。
本研究目的的关键技术,提供更variation-tolerant电路的设计。我们提出解决这个问题,在设计阶段的post-fabrication阶段。后者要有方法的可行性进行调整和规范快捷高效的框架,使post-silicon调谐变得更有吸引力。总结提出的技术,如左: