高手清帮忙看下VHDL AD控制

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adcontroller is
port( clk , eoc : in std_logic;
cs , sc , oe : out std_logic );
end adcontroller;
architecture state_machine of adcontroller is
type state_type is (idle ,start ,convert ,read1 , read2);
signal present_state , next_state : state_type;
begin
state_comb : process(present_state , eoc)
begin
case present_state is
when idle=>
cs<='1'; sc<='1'; oe<='1';
when start=>
cs<='0'; sc<='0'; oe<='1';
if (eoc='0') then next_state<=convert;
else next_state<=start;
end if;
when convert=>
cs<='0

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