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来源：百度知道 编辑：UC知道 时间：2024/05/25 10:56:14
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NTRODUCTION
The complexity and density of circuit cards commonly encountered today presents significant challenges in the test and inspection arena. Circuit cards with thousands of devices, in excess of 10,000 electrical nodes and 20 or more PCB layers are not unusual in modern design practices. Unfortunately, with the increase in complexity comes an increase in defect
opportunities. Conversely, with the increase in densities the ability to provide the adequate number of test points to enable traditional test strategies, such as In-Circuit Test (ICT),
to verify the structural integrity of complex circuit cards has diminished. This is further exacerbated by the widespread use of Ball-Grid-Array (BGA) packaging with concealed contacts, complicating the access problem. This lack of physical access has lead to extensive adoption of the IEEE 1149.1 boundary-scan standard. Also known as JTAG for the Joint Test Action Group hat initiated work on the subsequent stand
NTRODUCTION
The complexity and density of circuit cards commonly encountered today presents significant challenges in the test and inspection arena. Circuit cards with thousands of devices, in excess of 10,000 electrical nodes and 20 or more PCB layers are not unusual in modern design practices. Unfortunately, with the increase in complexity comes an increase in defect
opportunities. Conversely, with the increase in densities the ability to provide the adequate number of test points to enable traditional test strategies, such as In-Circuit Test (ICT),
to verify the structural integrity of complex circuit cards has diminished. This is further exacerbated by the widespread use of Ball-Grid-Array (BGA) packaging with concealed contacts, complicating the access problem. This lack of physical access has lead to extensive adoption of the IEEE 1149.1 boundary-scan standard. Also known as JTAG for the Joint Test Action Group hat initiated work on the subsequent stand
NTRODUCTION
的复杂性和密度电路卡遇到的今天带来了重大的挑战测试和检查舞台。电路卡，成千上万的设备，超过10,000电气节点和20个或更多的PCB层的不寻常的现代设计的做法。不幸的是，随着复杂性的增加来增加缺损
机会。相反，随着密度的能力，提供足够数量的测试点，使传统的测试策略，如在电路测试（信息和通信技术） ，
核查的结构完整性，复杂的电路卡已经减少。这进一步加剧了广泛使用的球网格阵列（ BGA ）包装带暗接触，复杂的访问问题。这种缺乏物理访问已导致广泛采用的IEEE 1149.1边界扫描标准。也被称为的JTAG的联合测试行动小组开始工作，帽子上的后继标准，该测试方法提供了非常高的测试覆盖的复杂数字电路卡通过一个简单的4线（ 5 -电线如果选用异步复位信号包括TRST ）接口称为测试访问端口（方案） ，减轻物理访问的问题。这项试验的战略一直主要用于
制造测试和系统内编程和配置在板级。然而，由于广泛的选择扫描路径管理器件，来自各种芯片供应商的能力边界扫描可扩展到系统的环境。此外，系统级边界扫描架构嵌入式边界扫描测试领域以及远程测试，诊断和配置。