求分频器 Verilog程序

module freq（out,clk,reset）;
input clk,reset;
output out;
reg out;
reg[2:0] count;
always @(posedge clk or negedge reset)
if(!reset)
begin
out<=1'b0;
cont<3'd0;
end
else if(count==3'd8)
begin
count<=3'd0;
out<=1'b1;
end
else
count<=count+1'b1;
endmodule