verilog hdl 计时程序

来源：百度知道 编辑：UC知道 时间：2024/05/15 16:38:12
这个程序的有些地方不是很懂，麻烦高手解释一下
计时
module count(clk,hour1,min1,sec1);
input clk;
output [7:0]hour1,min1,sec1;
reg [7:0]hour1,min1,sec1;
reg clk_1Hz,clk_2Hz, minclk,hclk;
always @(posedge clk)
begin
clk_2Hz<=~clk_2Hz;
end
always @(posedge clk_2Hz)
clk_1Hz<=~clk_1Hz;
always @(posedge clk_1Hz)
if(sec1==8'h59)
begin sec1<=0;
minclk<=1;
end
else begin
if(sec1[3:0]==9)
begin sec1[3:0]<=0;
sec1[7:4]<=sec1[7:4]+1;
end
else sec1[3:0]<=sec1[3:0]+1;
minclk<=0;
end
always @(posedge minclk)
begin if(min1==8'h59)
begin min1<=0;
hclk<=1;
end
else begin
if(min1[3:0]==9)
begin min1[3:0]<=0;
min1[7:4]<=min1[7:4]+1;

always @(posedge clk)
begin
clk_2Hz<=~clk_2Hz; //产生2hz的clock信号，周期为0.5s
end
always @(posedge clk_2Hz)
clk_1Hz<=~clk_1Hz; //产生1hz的clock信号，周期为1s

always @(posedge clk_1Hz)
if(sec1==8'h59) //产生秒针信号，数到60累加1
begin sec1<=0; //minclk为分针信号
minclk<=1;
end
else begin
if(sec1[3:0]==9)
begin sec1[3:0]<=0;
sec1[7:4]<=sec1[7:4]+1;
end
else sec1[3:0]<=sec1[3:0]+1;
minclk<=0;
end
always @(posedge minclk)
begin if(min1==8'h59) //产生分针信号，数到60累加1
begin min1<=0; //产生时针信号，数到60累加1
hclk<=1;
end
else begin
if(min1[3:0]==9)
begin min1[3:0]<=0;
min1[7:4]<=min1[7:4]+1;
end
else min1[3:0]&