FPGA十分频程序，用VHDL写！！急求!!!

我这个是可以实现多个分频的。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DVF IS
PORT(CLK:IN STD_LOGIC; ----时钟输入---
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); ----这个输入11111111-1010=1110101即是十分频----
FOUT:OUT STD_LOGIC); ----对CLK十分频后的输出----
END;
ARCHITECTURE ONE OF DVF IS
SIGNAL FULL:STD_LOGIC;
SIGNAL F_T:STD_LOGIC;

BEGIN
P_REG:PROCESS(CLK)
VARIABLE CNT8:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CNT8="11111111"THEN
CNT8:=D;
FULL<='1';
ELSE CNT8:=CNT8+1;
FULL<='0';
END IF;
END IF;
END PROCESS P_REG;
P_DIV:PROCESS(FULL)
VARIABLE CNT2:STD_LOGIC;
BEGIN
IF FULL'EVENT AND FULL='1' THEN
CNT2:=NOT CNT2;
IF CNT2='1' THEN
F_T<='1';
ELSE F_T<='0';
END IF;