Verilog编程高手帮忙看下

来源：百度知道 编辑：UC知道 时间：2024/05/15 10:28:04
夏宇闻老师的卷积器设计 我想将它在MODELSIM上仿真一下 但不管怎么弄 编译的时候总有一个错误 代码如下 用的是书上照搬的
module con1(address,indata,outdata,wr,nconvst,nbusy,enout1,enout2,CLK,reset,start);
input clk,
reset,
start,
nbusy;
output wr,
enout1,enout2,
nconvst,
address;
input[7:0] indata;
output[7:0] outdata;
wire nbusy;
reg wr;
reg nconvst,
enout1,
enout2;
reg[7:0] outdata;
reg[10:0] address;
reg[8:0] state;
reg[15:0] result;
reg[23:0] line;
reg[11:0] counter;
reg high;
reg[4:0] j;
reg EOC;
parameter h1=1,h2=2,h3=3;
parameter IDLE=9'b000000001,START=9'b000000010,NCONVST=9'b000000100,READ=9'b000001000,CALCU=9'b000010000,WRREADY=9'b000100000,WR=9'b001000000,WREND=9'b010000000,WAITFOR=9'b100000000;
parameter FAMX=20;
always@(posedge CLK)
if(!reset)
begin
state<=IDLE;
nconv

可以了朋友，是一些拼写错误，FMAX写成了FAMX、分号写成了冒号、还有貌似CLK的大小写是有区别的，帮你改好了，编译已经通过，就是没仿真，自己拿去用吧！
module con1(address,indata,outdata,wr,nconvst,nbusy,enout1,enout2,clk,reset,start);
input clk,
reset,
start,
nbusy;
output wr,
enout1,enout2,
nconvst,
address;
input[7:0] indata;
output[7:0] outdata;
wire nbusy;
reg wr;
reg nconvst,
enout1,
enout2;
reg[7:0] outdata;
reg[10:0] address;
reg[8:0] state;
reg[15:0] result;
reg[23:0] line;
reg[11:0] counter;
reg high;
reg[4:0] j;
reg EOC;
parameter h1=1,h2=2,h3=3;
parameter IDLE=9'b000000001,START=9'b000000010,NCONVST=9'b000000100,READ=9'b000001000,CALCU=9'b000010000,WRREADY=9'b000100000,WR=9'b001000000,WREND=9'b010000000,WAITFOR=9'b100000000;
parameter FMAX=20;
always@(posedge clk)
if(!reset)
begin
state<=IDL