VHDL错误

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity process_com is
port(p1: in bit;
p2: out bit);
end entity;

architecture catch of process_com is
signal p21, p12: bit:="0";
begin
coma:process(p1,p21)
begin
if (p1' event and p1='1') or (p21' event and p21='1')
then
p12=<'1' after 20ns;
'c' after 30ns;

end if;
end process coma;
comb:process(p12)
begin
if (p21' event and p21="1")
then
p21=<'1' after 10ns;
'0' after 20ns;
p2=<'1' after 30ns;
end if;
end process comb;
end catch;
谁还能帮我看看错哪儿了啊，
按照juzizhao的写法，出现
1）Error (10628): VHDL error at process_com.vhd(19): can't implement register for tw

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity process_com is
port(p1: in bit;
p2: out bit);
end entity;

architecture catch of process_com is
signal p21,p12: bit:='0';
begin
coma:process(p1,p21)
begin
if (p1' event and p1='1') or (p21' event and p21='1')
then
p12<='1' after 20ns,
'0' after 30ns;

end if;
end process coma;
comb:process(p12)
begin
if (p12' event and p12='1')
then
p21<='1' after 10ns,
'0' after 20ns;
p2<='1' after 30ns;
end if;
end process comb;
end catch;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;