vhdl 数字钟

use ieee.std_logic_1164.all;--顶层实体，用的是20Mhz的时钟
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity clock_shu is
port(
clk : in std_logic;
reset : in std_logic;
duan : out std_logic_vector(5 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end;

architecture a of clock_shu is
component count60
port(
carry : std_logic;
rst : std_logic;
times : out integer range 0 to 59;
full : out std_logic
);
end component;

component count24
port(
carry : in std_logic;
rst : in std_logic;
times : out integer range 0 to 23
--full : out std_logic
);
end component;

component i60bcd
port(
interg : in integer range 0 to 59;