UC知道verilog如何给输入信号？
来源：百度知道 编辑：UC知道 时间：2024/05/28 05:16:33
没信号怎么看波形呀，不知道怎么给输入信号，程序如下，但有错误，第一行和第四行，说A,B是不兼容声明
'timescale 1us/1ns
module AGC_wangxia(A,B,Alarm,Gain);
input A,B;
output Alarm;
output[3:0] Gain;
reg A,B;
reg Alarm;
reg[3:0] Gain;
initial
begin
Alarm=0;
Gain=1;
end
always #2 A=~A;
always #5 B=~B;
always @(posedge A or posedge B)
if(A==B)
begin
if(A==B==0)
Gain=(Gain<<1);
else if(Gain!=1)
Gain=(Gain>>1);
else Alarm=1;
end
endmodule
'timescale 1us/1ns
module AGC_wangxia(A,B,Alarm,Gain);
input A,B;
output Alarm;
output[3:0] Gain;
reg A,B;
reg Alarm;
reg[3:0] Gain;
initial
begin
Alarm=0;
Gain=1;
end
always #2 A=~A;
always #5 B=~B;
always @(posedge A or posedge B)
if(A==B)
begin
if(A==B==0)
Gain=(Gain<<1);
else if(Gain!=1)
Gain=(Gain>>1);
else Alarm=1;
end
endmodule
reg A,B; 改为wire A, B;
输入信号不能是reg类型
怎么给A,B信号，需要再额外写个测试程序如下
module test_AGC_wangxia；
reg A,B;
wire Alarm;
wire [3:0] Gain;
AGC_wangxia m1_(A,B,Alarm,Gain);
initial begin
A=0;
B=0;
end
always #10 A=~A;
always #20 B=~B;
endmodule
用modelsim就可以仿真了