vhdl改错，填空，急急急

来源：百度知道 编辑：UC知道 时间：2024/05/31 03:55:43
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY asm_led
PORT(clr,clk:IN std_logic;
led1,led2,led3:OUT std_logic);
END;
ARCHITECTURE a OF asm_led IS
BEGIN
_________states IS (s0,s1,s2,s3,s4,s5);
SIGNAL q: std_logic_vector(0 TO 2);
SIGNAL state:states;
p1:PROCESS(clk,=1________)
BEGIN
IF(clr=’0’) THEN state<=s0;
ELSIF(clk’event AND clk=’1’) THEN
CASE state IS
WHEN s0=>state: =s1;
WHEN s1=>state: =s2;
WHEN s2=>state: =s3;
WhEN s3=>state: =s4;
WHEN s4=>state: =s5;
WHEN s5=>state: =s0;
END CASE;
END IF;
END PROCESS p1;

p2:PROCESS(clr,_________)
BEGIN
IF clr=’0’ THEN led1<=’1’;led2<=’0’;led3<=’0’;
ELSE CASE state
WHEN s0=> led1<=’1’;led2<=’0’;led3<=’0’;
WHEN s1=> led1<=’0’;led2<=’1’;led3<=’0’;
WHEN s2=> led1<=’0’;led2<=’1’;led3<=’0’;
WHEN s3=> led1

TYPE
ns
state

改错
【3】：ENTITY asm_led “IS”

ARCHITECTURE a OF asm_led IS
BEGIN (去掉这个BEGIN)

p1:PROCESS(clk,“clr,”=1________)

P2中：
IF clr=’0’ THEN led1<=’1’;led2<=’0’;led3<=’0’； “END IF；”