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来源:百度知道 编辑:UC知道 时间:2024/05/03 19:51:16
线性分组编码是一类重要的纠错码,它主要用于降低误码率,提高数字信号传输的可靠性。本设计基于windows xp平台,采用MAX + Plus II软件中的图形编辑模块和文本编辑模块,运用VHDL对线性分组编码器的编码功能,进行组合逻辑电路设计以及VHDL设计,并对两种设计进行波形仿真。组合逻辑电路设计,是根据线性分组编码理论,利用与非门、触发器等逻辑器件搭建起来的电路原理图;VHDL设计,是将线性分组编码理论通过用VHDL描述,实现其编码功能。本设计针对(7,4)线性分组编码器的功能进行详细设计,当一组4位的信息序列进入编码器时,监督码元被加到信息码元之后,形成一组新的信息序列,此序列的前4位是信息码元,后3位是监督码元,3个监督位的作用就是实现检错与纠错。本设计通过两种不同方案设计出线性分组编码器,利用MAX+Plus II软件模拟了编码理论中一系列繁琐的算法,通过对比可知,理论值与实际波形相符,实现了线性分组编码器的功能。

Linear block code is an important kind of error correction code, which is used to reduce Bit Error Rate (BER) and so to improve the reliability of digital signal transfer. This design which is based on the WindowsXp platform, using Graphic editor and text editor of MAX+PLUS II, to design Linear block code through VHDL and Combinational logic. both of these realization are simulated. Combinational Logic design which based on the theory of Linear block code is the circuit map of Linear block code using AND-gate, OR-gate, Flip-flop and so on. VHDL design is the hardware description of the circuit map to make linear block code into realization. this design describes the function of (7,4) linear block code in detail. when a set of 4 serial bits signal flows into linear block code, check bits are added to the signal, thus, a new serial sequence is born, which the first 4 bits are information, the last 3 bits are check bits. Those 3 bits is used to discover and correct error bit. this des