UC知道谁帮忙翻译下我的自动化专业英语,关于CMOS
来源：百度知道 编辑：UC知道 时间：2024/05/19 19:10:12
This structure is less limited than the bipolar eduivalent
would be, but there are still some practical limits. One of these
is the combined resistance of the M05FETs in series. As a
result, CMOS totem poles are not made more than four inputs
high. Gates with more than four inputs are built as cascading
structures rather than single structures. However, the logic is
still valid.
Even with this limit, the totem pole structure still causes
some problems in certain applications. The pull-up and pull-down
resistances at the output are never the same, and can change significantly as the inputs change state, even if the output does not change logic states. The result is uneven and unpredictable rise and fall times for the output signal. This problem was addressed, and was solved with the buffered, or B-series CMOS gates.
The technique here is to follow the actual NAND gate with a pair of inverters, as shown in Fig. 3.4. Thus, th
would be, but there are still some practical limits. One of these
is the combined resistance of the M05FETs in series. As a
result, CMOS totem poles are not made more than four inputs
high. Gates with more than four inputs are built as cascading
structures rather than single structures. However, the logic is
still valid.
Even with this limit, the totem pole structure still causes
some problems in certain applications. The pull-up and pull-down
resistances at the output are never the same, and can change significantly as the inputs change state, even if the output does not change logic states. The result is uneven and unpredictable rise and fall times for the output signal. This problem was addressed, and was solved with the buffered, or B-series CMOS gates.
The technique here is to follow the actual NAND gate with a pair of inverters, as shown in Fig. 3.4. Thus, th
这个结构是有限的不足，比双极eduivalent 会，但还存在一些实际限制。一，这些是联合抵抗的m05fets在一系列。作为一个结果，图腾的CMOS极不作出了四个多投入高的。盖茨与四年多的投入，是建立在作为级联结构，而非单一的结构。然而，逻辑是： 仍然有效。
即使这个限额，图腾柱结构，还是引起了一些题，在某些应用。下拉式和下拉式电阻在输出从来都不是相同的，并能显着改变，作为国家投入的变化，即使输出不会改变的逻辑。结果是不平衡的和难以预料的上升和下降时间为输出信号。这个问题已经解决，并解决了与缓冲，或B系列的CMOS盖茨。
该技术在这里，是按照实际的NAND门，与一对逆变器，显示在图。 3.4 。因此，输出将始终驱使一个单一的晶体管，无论是P通道或N通道。因为他们是作为密切配合，尽可能的输出电阻的大门将永远是一样的，和信号的行为，因此，更可预见。