VHDL问题

来源：百度知道 编辑：UC知道 时间：2024/05/16 04:46:35
process(counter,hv)
begin
if (state=WRITERAM and counter=1)then
if(hv='0')then
char_addr<=conv_std_logic_vector(counter+23,6);
else char_addr<=conv_std_logic_vector(counter,6);
elsif(state=WRITERAM and counter<81 and counter>1)then
char_addr<=conv_std_logic_vector(counter,6);
else char_addr<="000000";
end if;
end process;
编译时出错Error: VHDL syntax error at lcd.vhd(162) near text "elsif"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a sequenial statement, 是什么意思？

少了一个end if；见程序：
process(counter,hv)
begin
if(state=WRITERAM and counter=1)then
if(hv='0')then
char_addr<=conv_std_logic_vector(counter+23,6);
else
char_addr<=conv_std_logic_vector(counter,6);
end if;
elsif(state=WRITERAM and counter<81 and counter>1)then
char_addr<=conv_std_logic_vector(counter,6);
else
char_addr<="000000";
end if;
end process;