UC知道请帮忙翻译一段电子专业英语
来源：百度知道 编辑：UC知道 时间：2024/05/27 00:54:17
the rise and fall times limit zhe response by not reaching the next logic level in time to be recognized.the rise and fall times can be somewhat cantrolled through good layout to reduce capacitance and inductance,by limiting the number of stages that are driven ,and by the occasional use of a pull-up resitor in the output circuits.
to summarize,the problems with digital circuits increase rapidly as the toggle frequencies are approached.much difficulty is avoided if the operating ferquencies are limited to one half of the minimum toggle value and if the setup times are increased by a factor of 2 or 3 over the manufacturer is stated minimum values
to summarize,the problems with digital circuits increase rapidly as the toggle frequencies are approached.much difficulty is avoided if the operating ferquencies are limited to one half of the minimum toggle value and if the setup times are increased by a factor of 2 or 3 over the manufacturer is stated minimum values
上升和下降时间限制哲的反应没有达到在今后的逻辑水平的时间才能确认。上升和下降时间可以有所cantrolled通过良好的布局，以减少电容和电感，限制了若干阶段的驱动，并偶尔使用拉resitor在输出电路要总结的问题，与数字电路迅速增加的切换频率接近。很多困难是可以避免的，如果经营ferquencies是有限的二分之一切换的最低值， 如果安装时间增加了2个或3个以上的制造商表示最低值......应该是这样翻译的.......