UC知道关于vhdl 数据移位问题
来源：百度知道 编辑：UC知道 时间：2024/06/12 10:23:19
case mode(3)&disp_mode(1 downto 0) is
when "000" =>
case temp_state is
when "1000" => sig_data <= data;
when "0111" => sig_data <= "1" & data(6 downto 0);
when "0110" => sig_data <= "11" & data(5 downto 0);
when "0101" => sig_data <= "111" & data(4 downto 0);
when "0100" => sig_data <= "1111" & data(3 downto 0);
when "0011" => sig_data <= "11111" & data(2 downto 0);
when "0010" => sig_data <= "111111" & data(1 downto 0);
when "0001" => sig_data <= "1111111" & data(0) ;
when "0000" => sig_data <= "11111111";
when others => null;
end case;
when "001" =>
case temp_state is
when "1000" => sig_data <= data;<
when "000" =>
case temp_state is
when "1000" => sig_data <= data;
when "0111" => sig_data <= "1" & data(6 downto 0);
when "0110" => sig_data <= "11" & data(5 downto 0);
when "0101" => sig_data <= "111" & data(4 downto 0);
when "0100" => sig_data <= "1111" & data(3 downto 0);
when "0011" => sig_data <= "11111" & data(2 downto 0);
when "0010" => sig_data <= "111111" & data(1 downto 0);
when "0001" => sig_data <= "1111111" & data(0) ;
when "0000" => sig_data <= "11111111";
when others => null;
end case;
when "001" =>
case temp_state is
when "1000" => sig_data <= data;<
用数组如何？
===================
variable tmp:std_logic_vector(7 downto 0);
就像你用data数组一样。用数组把各个状态整合判断的话，写出来可能会少几行。真要大幅度改进的话，还要看看有没有什么好方法吧CASE中的各个状态优化一下 。
关于你说的资源为题，可以看一下这个地方，讲的比较清楚。希望对你有用
http://www.lwwzx.com/Freepaper/6281.htm