帮忙翻译vhdl到verilog

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cmdreg IS
PORT (
RESET : IN std_logic;
MasterClear : IN std_logic;
WriteDataIn : IN std_logic_vector(7 DOWNTO 0);
LoadCmdReg : IN std_logic;
CLK : IN std_logic;
CmdOut : INOUT std_logic_vector(7 DOWNTO 0) );
END cmdreg;
ARCHITECTURE rtl OF cmdreg IS
BEGIN
CmdRegProc: PROCESS ( LoadCmdReg, WriteDataIn, CmdOut, RESET,MasterClear, CLK )

VARIABLE next_CmdOut : std_logic_vector(7 DOWNTO 0);

BEGIN

IF ( LoadCmdReg = '1' ) THEN

next_CmdOut := WriteDataIn;

ELSE

next_CmdOut := CmdOut;

END IF;

IF ( (RESET = '1') OR (MasterClear = '1') ) THEN -- Asynchronous clear

CmdOut <= "00000000";

ELSIF ( CLK'EVENT AND (CLK = '0') ) THEN

module cmdreg(RESET,WriteDataIn,MasterClear,LoadCmdReg,CLK,CmdOut);
input RESET,MasterClear,LoadCmdReg,CLK;
input [7:0] WriteDataIn;
inout [7:0] CmdOut;

reg [7:0] next_CmdOut,CmdOut;
always @ (posedge CLK)
begin

if(LoadCmdReg)
next_CmdOut <= WriteDataIn;
else
next_CmdOut <= CmdOut;
end

always @ (negedge CLK)
begin
if(RESET || MasterClear)
CmdOut <= 'b00000000;
else
CmdOut <= next_CmdOut;
end
endmodule
谁告诉你不可以定义为REG你拿综合器去看看。

图书馆的IEEE ;

使用IEEE.std_logic_1164.ALL ;

实体cmdreg是

端口（

复位：在std_logic ;

MasterClear ：在std_logic ;

WriteDataIn ：在std_logic_vector （ 7 DOWNTO 0 ） ;

LoadCmdReg ：在std_logic ;

时钟：在std_logic ;

CmdOut ： INOUT std_logic_vector （ 7 DOWNTO 0 ） ） ;

完cmdreg ;

建筑的RTL的cmdreg是

动工