用VHDL编写N分频器

分频没必要一定用锁相环啊，普通分频就可以了啊，锁相环一般是用倍频的，我把代码给你，你研究一下，这个电路我前两天刚调试成功
-----------------------------------------------------------------------
-- This section contains clock manager.
-----------------------------------------------------------------------
IBUFG_clock : IBUFG
generic map (
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only)
IOSTANDARD => "DEFAULT")
port map (
O => clkin_buf, -- Clock buffer output
I => clk_in -- Clock buffer input (connect directly to top-level port)
);

BUFG_clk_sys : BUFG
port map (
O =>clk_sys, -- Clock buffer output
I => CLK0 -- Clock buffer input
);

BUFG_clk_fx : BUFG
port map (
O => TX_CLK, -- Clock buffer output
I => CLKFX -- Clock