，用VHDL程序编制一个同步计数器。要求模为24，具有异步复位，

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity count24 is
port(
clr : in STD_LOGIC;
clk : in STD_LOGIC;
d : out STD_LOGIC_VECTOR(4 downto 0));
end count24;

architecture beh1 of count24 is
signal cnt:integer range 0 to 23 :=0;
begin
process(clk,clr)
begin
if(clr='1')then
cnt<=0;
else
if(clk'event and clk='1')then
if cnt=0 then
cnt<=23;
else
cnt<=cnt-1;
end if;
end if;
end if;
end process;
d<="00000" when cnt=0 else
"00001" when cnt=1 else
"00010" when cnt=2 else
"00011" when cnt=3 else
"00100" when cnt=4 else
"00101" when cnt=5 else
"00110" when cnt=6 else
"00111" when cnt=7 else
&quo