UC知道muxplus编译vhdl语言出现错误
来源：百度知道 编辑：UC知道 时间：2024/06/22 05:25:11
源代码：
LIBRARY IEEE;
USE IEEE STD_LOGIC_1164.ALL;
ENTITY mux2 IS
PORT(d0:IN STD_LOGIC_VECTOR(3DOWNTO0);
d1:IN STD_LOGIC_VECTOR(3DOWNTO0);
sel:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3DOWNTO0));
END mux2;
ARCHITECTURE rtl OF mux2 IS
BEGIN
PROCESS(d0,d1,sel)
BEGIN
IF(sel='1')THEN
q<=d0;
ELSE
q<=d1;
END IF;
END PROCESS;
END rtl;
编译时出现一个错误：Expected ASSERT,CONSTANT,DEFINE,DESIGN,FUNCTION,IF,OPTIONS,PARAMETERS,SUBDESIGN,or TITLE but found a symbolic name "LIBRABRY"
LIBRARY IEEE;
USE IEEE STD_LOGIC_1164.ALL;
ENTITY mux2 IS
PORT(d0:IN STD_LOGIC_VECTOR(3DOWNTO0);
d1:IN STD_LOGIC_VECTOR(3DOWNTO0);
sel:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3DOWNTO0));
END mux2;
ARCHITECTURE rtl OF mux2 IS
BEGIN
PROCESS(d0,d1,sel)
BEGIN
IF(sel='1')THEN
q<=d0;
ELSE
q<=d1;
END IF;
END PROCESS;
END rtl;
编译时出现一个错误：Expected ASSERT,CONSTANT,DEFINE,DESIGN,FUNCTION,IF,OPTIONS,PARAMETERS,SUBDESIGN,or TITLE but found a symbolic name "LIBRABRY"
我已经帮你改过,并编译成功了.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux2 IS
PORT(
d0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
d1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sel : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END mux2;
ARCHITECTURE rtl OF mux2 IS
BEGIN
PROCESS(d0,d1,sel)
BEGIN
IF(sel='1')THEN
q<=d0;
ELSE
q<=d1;
END IF;
END PROCESS;
END rtl;
第二行IEEE和STD_LOGIC_1164之间少了一个点