UC知道VHDL CASE语句描述4选1选择器程序
来源：百度知道 编辑：UC知道 时间：2024/06/20 10:37:37
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux4_3 IS
PORT( cdata : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC );
END mux4_3 ;
ARCHITECTURE rt1_mux4 OF mux4_3 IS
SIGNAL temp_sel : INTEGER RANGE O TO 3 ;
BEGIN
cumx4_3 : PROCESS (cdata,sel)
BEGIN
temp_sel <= '0';
IF ( sel (0) = '1' ) THEN
temp_sel <= temp_sel + 1 ;
END IF ;
IF ( sel (1) ='1') THEN
temp_sel <= temp_sel +2;
END IF;
CASE temp_sel IS
WHEN 0 => q <= cdata (0);
WHEN 1 => q <= cdata (1);
WHEN 2 => q <= cdata (2);
WHEN 3 => q <= cdata (3);
WHEN OTHERS => q <= '0';
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux4_3 IS
PORT( cdata : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC );
END mux4_3 ;
ARCHITECTURE rt1_mux4 OF mux4_3 IS
SIGNAL temp_sel : INTEGER RANGE O TO 3 ;
BEGIN
cumx4_3 : PROCESS (cdata,sel)
BEGIN
temp_sel <= '0';
IF ( sel (0) = '1' ) THEN
temp_sel <= temp_sel + 1 ;
END IF ;
IF ( sel (1) ='1') THEN
temp_sel <= temp_sel +2;
END IF;
CASE temp_sel IS
WHEN 0 => q <= cdata (0);
WHEN 1 => q <= cdata (1);
WHEN 2 => q <= cdata (2);
WHEN 3 => q <= cdata (3);
WHEN OTHERS => q <= '0';
帮你注释一下：
temp_sel <= '0'; --把0给temp-sel
IF ( sel (0) = '1' ) THEN
temp_sel <= temp_sel + 1 ; ——如果sel的低位为0，则temp_sel加1
END IF ;
IF ( sel (1) ='1') THEN
temp_sel <= temp_sel +2;——如果sel的低位向上第二位为1，则temp_sel加2
END IF;
效果一样，你那个更直观。
这个只是按照二进制翻译成十进制