UC知道VHDL跑程序出错 求高手解
来源：百度知道 编辑：UC知道 时间：2024/05/25 08:49:55
entity whileexp is
port(a:in bit_vector(0 to 3);
out1: out bit_vector(0 to 3));
end entity whileexp;
architecture art of whileexp is
begin
process(a) is
variable b:bit;
variable i:integer;
begin
i:=0;
while i<3 loop
b:=a(2-i)and b;
out1(i)<=b;
end loop;
end process;
end architecture art;
unsupported feature error: loops other than 'for loops' are not supported at line 12 in file
i：=i+1；后 情况还是一样
unsupported feature error: loops other than 'for loops' are not supported at line 12 in file
port(a:in bit_vector(0 to 3);
out1: out bit_vector(0 to 3));
end entity whileexp;
architecture art of whileexp is
begin
process(a) is
variable b:bit;
variable i:integer;
begin
i:=0;
while i<3 loop
b:=a(2-i)and b;
out1(i)<=b;
end loop;
end process;
end architecture art;
unsupported feature error: loops other than 'for loops' are not supported at line 12 in file
i：=i+1；后 情况还是一样
unsupported feature error: loops other than 'for loops' are not supported at line 12 in file
你变量i的值不能变化，i：=i+1；
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity whileexp is
port(a:in bit_vector(0 to 3);
out1: out bit_vector(0 to 3));
end entity whileexp;
architecture art of whileexp is
begin
process(a) is
variable b:bit;
variable i:integer;
begin
i:=0;
while i<3 loop
b:=a(2-i)and b;
out1(i)<=b;
i:=i+1;
end loop;
end process;
end architecture art;
仿真出来没有问题的，你看下是不是你的库和程序包的定义有误