用VHDL编写一个计数器，从0记到7后自动减，减为0时自动加到7，如此循环，哪位高手帮忙解决，尽快，谢谢啦

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnt8 is port
{ rst : in std_logic;
clk : in std_logic;
cntout : out std_logic_vector(2 downto 0)
}
end cnt8;

architecture a of cnt8 is
signal cnt : integer:=0 ;
begin
process(rst, clk)
begin
if( rst = '1') then
cnt <= (others=>'0');
elsif rising_edge(clk) then
if cnt < 8 then
cnt <= cnt +1;
else
cnt <= 0;
end if;
end if;
end process;
cntout <= conv_std_logic_vector(cnt, 3);
end a;