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来源：百度知道 编辑：UC知道 时间：2024/05/01 08:29:30
This article describes how to divide clocks by 1.5, 2.5,and by 3,and 5 with a 50% duty-cycle output.Dividing an incoming clock frequency by any integer number is triviak,and division by any even number always generates a 50% duty cycle output.However sometimes it is necessary to generate a 50% duty cycle frequency that is not an even integer sub-multiple of the source clock.
HOW THEY WORK
Each circuit assumes a 50/50 duty cycle of the incoming clock,otherwise the fractional divider output will jitter,and the integer divider will have unequal duty cycle.All four circyits use comebinatorial feedback around a look-up table,which works perfectly and is glitch-free,butmay cause your circult simulator to fall.
These circuits have a look-up table input driven from the clock signal,with minimal skew between the A and B inputs.The chosen vertical clock line must,therefore,also have access to a LUT input.This is best achieved by coding the design as a Hard Macro.
Dicide
HOW THEY WORK
Each circuit assumes a 50/50 duty cycle of the incoming clock,otherwise the fractional divider output will jitter,and the integer divider will have unequal duty cycle.All four circyits use comebinatorial feedback around a look-up table,which works perfectly and is glitch-free,butmay cause your circult simulator to fall.
These circuits have a look-up table input driven from the clock signal,with minimal skew between the A and B inputs.The chosen vertical clock line must,therefore,also have access to a LUT input.This is best achieved by coding the design as a Hard Macro.
Dicide
有点多，给你个网址，自己翻译吧。一次别贴的太多，翻译的结果还要顺一下才好。
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