vhdl 做branch equal BEQ

来源：百度知道 编辑：UC知道 时间：2024/09/21 18:11:38
architecture behavioral of beq IS
begin
if (x = y) AND ( c_in=1) then z =: 1;
else z =: 0;
end if;

end behavioral;

就是 Z = 1 if X=Y, and Cin =1 否则Z =0； Cout=0
编译错误提示
Error (10500): VHDL syntax error at BEQ4.vhd(15) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
请问高手 怎么改 谢谢

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Entity time is
port(
clk :in std_logic;
A :in std_logic;
B :in std_logic;
C :in std_logic;
cl :out std_logic;
month :buffer std_logic_vector(3 downto 0);
date :buffer std_logic_vector(4 downto 0);
hou :buffer std_logic_vector(4 downto 0);
min :buffer std_logic_vector(5 downto 0);
sec :buffer std_logic_vector(5 downto 0);
msec :buffer std_logic_vector(6 downto 0)
);
end time;

Architecture behave of time is
signal g:integer range 0 to 40;--DAYS OF EVERY MONTH
signal l:integer range 0 to 40;
signal cod:std_logic;--
signal coh:std_logic;
signal com:std_logic;
signal s :std_logic;--S=1 WHEN SECOND<20 USED FOR ALARM
signal cos:std_log