急问VHDL程序 双向移位寄存器程序

来源：百度知道 编辑：UC知道 时间：2024/05/21 07:09:57
如题目，请给详细程序，不要连接
以LIBRARY ieee开始
最好答案再补分，谢谢了。
很急。

--VHDL for Bidirectional Shift Register

library IEEE;
use IEEE.std_logic_1164.all;

entity sreg is
port (
d: in std_logic_vector(3 downto 0);
ld, sl, sr: in std_logic;
clk: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end sreg;

architecture sreg_arch of sreg is
signal reg: std_logic_vector(3 downto 0);
begin
process(clk) begin
if clk'event and clk = '1' then
if ld ='1' then
if sl = '1' then
reg <= reg(2 downto 0) & d(0);
elsif sr = '1' then
reg <= d(3) & reg(3 downto 1);
else
reg <= d;
end if;
end if;
end if;
end process;

q <= reg;
end sreg_arch;

俺不知道噢~~~~可怜的娃。自己在网上找下不就知道拉~~

VHDL: Bidirectional Bus
download from: http://www.fpga.com.cn

bidir.vhd (Tri-state bus impl