有懂VHDL语言的吗？

entity sel4_1 is
port(input:in std_logic_vector(1 downto 0);
clk:in std_logic;
a,b,c,d:in std_logic;
output:out std_logic
);
end entity;

architecture bhv of sel4_1 is
begin
process(clk)
begin
--该段可用case替换，建议运行时将此行删除
if input="00" then output<=a;
elseif input="01" then output<=b;
elseif input="10" then output<=c;
elseif input="11" then output<=d;
end if;
--到此
end process;
end bhv;

--可替换上面的if语句
case input is
when "00"=> output<="a";
when "01"=> output<="b";
when "10"=> output<="c";
when "11"=> output<="d";
when others=> null;
end case;

上面可是我手打的啊