集成电路版图的全自动布局布线

来源:百度知道 编辑:UC知道 时间:2024/05/25 04:46:55
哪位高人可以解释一下,集成电路版图的自动布局布线,到底怎么回事?如何用Cadencep实现!

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先给你一个目录吧 english

Synthesis, Place & Route
Ketan Joshi
Director of Marketing, SP&R
Design Concept to Implementation
Design Implementation Plan
Productive Design Plan with Cadence SP&R
Productive Design Plan with Cadence SP&R
Productive Design Plan with Cadence SP&R
Ambit BuildGates Quick Reference Card
What is it?
A logic synthesis tool
Like conventional synthesis, with greater performance and capacity
Who is the Typical User?
Logic designers using ASIC or COT flows
Why is it Better?
Higher performance/capacity
Superior QoR
Integrated Static Timing sign-off
Integrated Chip Synthesis and STA
Ambit BuildGates: Comprehensive Synthesis
Verilog, VHDL, EDIF
Integrated, Sign-off timing engine
Time Budgeting
Graphical UI
Distributed synthesis
AmbitWare
Test Synthesis
TCL - user interface
SDF,GCF, PDEF
Sun, HP, IBM