UC知道水帮忙翻译一下如下材料？
来源：百度知道 编辑：UC知道 时间：2024/06/23 07:37:47
The C55x architecture achieves power-efficient performance through
increased parallelism and complete focus on reduction in power dissipation. The CPU supports an internal bus structure composed of:
one program bus
three data read buses two data write buses
additional buses dedicated to peripheral and DMA activity
These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of CPU activity.
不要用翻译软件翻！！！！这是电子类的文章。
increased parallelism and complete focus on reduction in power dissipation. The CPU supports an internal bus structure composed of:
one program bus
three data read buses two data write buses
additional buses dedicated to peripheral and DMA activity
These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of CPU activity.
不要用翻译软件翻！！！！这是电子类的文章。
该c55x建筑达到省电的表现，通过
增加并行性和完成的重点在减少功率耗散。支持的CPU内部总线结构，人员组成：
一个程序巴士
3数据读取巴士两个数据写入巴士
额外的巴士专用周边和DMA活动
这些巴士提供有能力执行最多三个数据读取和两个数据写在一个单一的周期。在并行， DMA控制器可以执行最多两个数据传输，每个周期独立的CPU活动。