利用VHDL语言设计一个十六进制计数器?

-- A asynchronous reset;;enable up; 8421BCD counter
-- module=60;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY cntm60v IS
PORT
(en: IN std_logic;
clear: IN std_logic;
clk: IN std_logic;
cout: out std_logic;
qh: buffer std_logic_vector(3 downto 0);
ql: buffer std_logic_vector(3 downto 0));
END cntm60v;
ARCHITECTURE behave of cntm60v IS
BEGIN
cout<='1' when(qh="0000" and ql="1001" and en='1')else'0';
PROCESS(clk,clear)
BEGIN
IF(clear='0')THEN
qh<="0000";
ql<="0000";
elsif(clk'EVENT AND CLK='1')THEN
if(en='1')then
if(ql=9)then
ql<="0000";
if(qh=5)then
qh<="0000";
else
qh<=qh+1;
end if;
else
ql<=ql