vhdl语言

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity xianshi is
port (clk:in std_logic;
inshu:in std_logic_vector(7 downto 0);
led:out std_logic_vector(6 downto 0);
wx:out std_logic_vector(3 downto 0) );
end xianshi ;
architecture one of xianshi is
signal clk2:std_logic;
signal s1:std_logic_vector(1 downto 0);
signal a,b,c,d,s2:std_logic_vector(3 downto 0);
begin
p1:process(clk,clk2)
begin
if clk'event and clk='1' then
clk2<=not clk2;
end if;
end process;
p2:process(clk,clk2)
begin
if clk'event and clk='1' then
if clk2='1' then a<=inshu(3 downto 0);
b<=inshu(7 downto 4);
else c<=inshu(3 downto 0);
d<=inshu(7 downto 4);
end if;
end if;
end process p2;
p3:process (s1,clk)
begin
if clk'event a

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