UC知道外文翻译的最后一段话，100分悬赏，请大家帮忙！
来源：百度知道 编辑：UC知道 时间：2024/06/12 00:53:03
谢绝软件翻译，这是关于AD574A的最后一段说明，如果有AD574A中文说明书的也请大家帮忙找找。我会加分！
The control signals CE, CS, and R/C control the operation of
the converter. The state of R/C when CE and CS are both
asserted determines whether a data read (R/C = 1) or a convert
(R/C = 0) is in progress. The register control inputs AO and
12/8 control conversion length and data format. The AO line is
usually tied to the least significant bit of the address bus. If a
conversion is started with AO low, a full 12-bit conversion cycle
is initiated. If AO is high during a convert start, a shorter 8-bit
conversion cycle results. During data read operations, AO determines
whether the three-state buffers containing the 8 MSBs of
the conversion result (AO = 0) or the 4 LSBs (AO = 1) are
enabled. The 12/8 pin determines whether the output data is
to be organized as two 8-bit words (12/8 tied to DIGITAL
COMMON) or a single 12-bit word (12/8 tied to VLOGIC). The
The control signals CE, CS, and R/C control the operation of
the converter. The state of R/C when CE and CS are both
asserted determines whether a data read (R/C = 1) or a convert
(R/C = 0) is in progress. The register control inputs AO and
12/8 control conversion length and data format. The AO line is
usually tied to the least significant bit of the address bus. If a
conversion is started with AO low, a full 12-bit conversion cycle
is initiated. If AO is high during a convert start, a shorter 8-bit
conversion cycle results. During data read operations, AO determines
whether the three-state buffers containing the 8 MSBs of
the conversion result (AO = 0) or the 4 LSBs (AO = 1) are
enabled. The 12/8 pin determines whether the output data is
to be organized as two 8-bit words (12/8 tied to DIGITAL
COMMON) or a single 12-bit word (12/8 tied to VLOGIC). The
你好，我帮你翻译好了，如下，请查阅，AD574A是一个模数转换的元件。相关datasheet下载地址是：
http://www.datasheetarchive.com/ADC574A-datasheet.html 点第一个PDF文档即可。
查外文资料最好不要用百度，推荐google,一搜就有。
翻译如下:
控制信号CE,CS和R/C控制转换器的运算。当CE或者CS有效后“R/C”这个信号的状态决定一个数据是处于读（R/C = 1，高电平）或者处于转换（(R/C = 0，低电平）状态。寄存器控制A0的输入，12/8这个信号控制转换长度和数据格式。A0这个信号线通常连地址总线最低有效位。如果转换开始时A0为低，则开始一个全12位的转换，如果数据转换开始时，A0为高电平，结果将是转换短字节的8位。在数据读操作过程中，A0决定三态缓冲器是否包含转换高8 位的结果(AO = 0)，或者使能低4位 (AO = 1)。12/8这个引脚决定输出数据是否组合成两个8位的字（1个字=8个位,数电你是知道的哈。）（ 12/8这个信号连到DIGITALCOMMON），或者一个单个的12位的数据(12/8这个信号连到 VLOGIC)。12/8引脚不是兼容TTL电平的引脚，必须硬件连接到VLOGIC或者 DIGITAL COMMON。在8位模式，当A0为高电平，地址编址包含从最低4位补0的地址。这个组合允许数据线可以直接叠加到直接的8位接口而无需额外的三态缓冲器。当数据出于“读”状态时候，不建议A0的状态有改变，异步使能或禁止三态缓冲器转换次数可能会导致内部总线争夺控制权，潜在的会对AD574A元件造成损害。