UC知道谁能帮我翻译一下下面的文字
来源：百度知道 编辑：UC知道 时间：2024/05/03 07:00:49
A hard-wired logic block (HLB) is created by replacing
some programmable connections with simple metal
wires, or hard-wired connections, between logic blocks [2,
3]. Since a metal wire incurs a much smaller delay and
requires less area than a programmable connection, FPGAs
built using HLBs have the potential to be both smaller and
faster than FPGAs in which all connections are programmable.
In this work, as in [2,3], we will consider only HLBs
composed of look-up tables (LUTs). Figure 2 illustrates
both an example HLB composed of three four-input LUTs
(4-LUTs) hard-wired in a chain and a circuit implemented
with this HLB.
some programmable connections with simple metal
wires, or hard-wired connections, between logic blocks [2,
3]. Since a metal wire incurs a much smaller delay and
requires less area than a programmable connection, FPGAs
built using HLBs have the potential to be both smaller and
faster than FPGAs in which all connections are programmable.
In this work, as in [2,3], we will consider only HLBs
composed of look-up tables (LUTs). Figure 2 illustrates
both an example HLB composed of three four-input LUTs
(4-LUTs) hard-wired in a chain and a circuit implemented
with this HLB.
一个硬联线逻辑块(HLB) 由替换创造 与简单的金属的一些可编程序的连接 导线, 或硬联线连接, 在逻辑块[ 2 之间, 3] 。因为金属线招致一更小延迟和 比可编程序的连接要求较少区域, FPGAs 修造使用HLBs 有潜力更小和 快速地比所有连接是可编程序的FPGAs 。 在这工作, 作为[ 2,3 ], 我们将考虑唯一HLBs 组成由查寻表(LUTs) 。图2 说明 例子HLB 组成由三四输入LUTs (4-LUTs) 硬联线在链子和电路被实施 与这HLB 。