UC知道麻烦大侠帮我翻译一下以下DSP的英文文章,好的加分
来源：百度知道 编辑：UC知道 时间：2024/05/14 11:29:47
This paper describes a new all-hardware technique for real-time interface of standard DSP devices to analogue to digital converters
(ADCs), and an associated ASIC system that has been designed to implement the technique. The system is based on a double buffer approach
and uses a phase-locked loop unit to control its synchronous parts. It is appropriate for real-time implementation of DSP algorithms that use
the block processing approach. The double buffer is facilitated by two on-chip 1 k £ 16 k bit SRAM blocks, as appropriate for a predefined
data frame size of 1024 samples. The system facilitates continuous sampling of the incoming analogue signals, via an ADC, and stores the
data in one of the RAMs. Concurrently, the DSP retrieves data stored in the second RAM from previous sampling interval, and processes it.
The approach eliminates the need for interrupt service and data collection routines and thus alleviates the design burden of real-time DSP<
(ADCs), and an associated ASIC system that has been designed to implement the technique. The system is based on a double buffer approach
and uses a phase-locked loop unit to control its synchronous parts. It is appropriate for real-time implementation of DSP algorithms that use
the block processing approach. The double buffer is facilitated by two on-chip 1 k £ 16 k bit SRAM blocks, as appropriate for a predefined
data frame size of 1024 samples. The system facilitates continuous sampling of the incoming analogue signals, via an ADC, and stores the
data in one of the RAMs. Concurrently, the DSP retrieves data stored in the second RAM from previous sampling interval, and processes it.
The approach eliminates the need for interrupt service and data collection routines and thus alleviates the design burden of real-time DSP<
这纸描绘a新完全-为标准DSP装置的向向数字的使转变的人((ADCs)和一已经是的结合ASIC系统相
似物实时-界面硬件技术设计执行技术.系统基于一双缓冲存储器接近的和使用阶段-使一个圈单
位不能动控制它的同时发生的零件.它是适合于使用块处理接近的DSP算法的实时-工具.双缓冲存
储器被二在-芯片1千上-方便£当为一预先定义数据占用1024样品的结构大小时,16千小块
SRAM堵住.系统方便经由一ADC进来的相似物信号的连续取样和在公羊之一中储藏数据.同时发生
地,DSP找回在从前一取样时间间隔第二随机存取存储中储藏数据和加工它.接近至于软件发展消
灭需要中断服务和数据收集例行工作和因此减轻设计实时-DSP系统的负担.它也建议使用的对DSP
装置的完整力量有利和提供更快处理和潜在地更高和准确取样频率.在这纸中描绘设计代表一分
离的ASIC系统的数字的核心的解决方案.数字的核心可以什么地方占用,是集成到一紧挨着一DSP
核心专一SoC解决方案中.q 2002Elsevier科学B.V.版权所有.块处理,那里时间-领土信号样品被
变为数据的结构当缓冲被是一块加工的是一特别给予重要表现的对于涉及讲话处理[[11]应用众
所周知实时-数字的信号处理技术.在这样DSP系统中,向ADC数字的信号处理器的内衬和数据收集