UC知道vhdl消抖程序意思
来源：百度知道 编辑：UC知道 时间：2024/05/26 13:03:29
library ieee;
use ieee.std_logic_1164.all;
entity xiaodou is
port(clk,input: in std_logic;
output: out std_logic);
end xiaodou;
architecture xiaodou_arc of xiaodou is
signal cp:std_logic;
signal count:integer range 0 to 3;
begin
process(clk)
begin
if(clk'event and clk='1') then
if(input='1')then
if(count=3)then count<=count;
else count<=count+1;
end if;
if(count=2)then cp<='1';
else cp<='0';
end if;
else count<=0;
end if;
end if;
output<=cp;
end process;
end xiaodou_arc
帮我解释下上面的消抖程序，说说消抖的原理额。
use ieee.std_logic_1164.all;
entity xiaodou is
port(clk,input: in std_logic;
output: out std_logic);
end xiaodou;
architecture xiaodou_arc of xiaodou is
signal cp:std_logic;
signal count:integer range 0 to 3;
begin
process(clk)
begin
if(clk'event and clk='1') then
if(input='1')then
if(count=3)then count<=count;
else count<=count+1;
end if;
if(count=2)then cp<='1';
else cp<='0';
end if;
else count<=0;
end if;
end if;
output<=cp;
end process;
end xiaodou_arc
帮我解释下上面的消抖程序，说说消抖的原理额。
这其实是用一个计数器来判断输入的脉冲的宽度，如果宽度大于3个脉冲，则认为这次输入有效，输出一个脉冲宽度的脉冲来替代输入信号，否则认为该次输入无效！
library ieee;
use ieee.std_logic_1164.all;
entity xiaodou is
port(clk,input: in std_logic;
output: out std_logic);
end xiaodou;
architecture xiaodou_arc of xiaodou is
signal cp:std_logic;
signal count:integer range 0 to 3;
begin
process(clk)
begin
if(clk'event and clk='1') then 检测上升沿
if(input='1')then 如果有输入信号
if(count=3)then count<=count; 当计数达到3时，保持计数值不变
else count<=count+1; 当其小于3时，进行加1处理
end if;
if(count=2)then cp<='1'; 如果计数达到2，cp置1
else cp<='0'; 其余情况全部为0
end if;
else count<=0; 如果计数出现非法状况，进行清零复位
end if;
end if;
output<=cp; 信号输出
end process;
end xiaodou_arc