用VHDL语言设计一个3输入的多数表决器

-- Three-input Majority Voter
-- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.
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ENTITY maj IS
PORT(a,b,c : IN BIT; m : OUT BIT);
END maj;
--Dataflow style architecture
ARCHITECTURE concurrent OF maj IS
BEGIN
--selected signal assignment statement (concurrent)
WITH a&b&c SELECT
m <= '1' WHEN "110"|"101"|"011"|"111",'0' WHEN OTHERS;
END concurrent;

--Structural style architecture
ARCHITECTURE structure OF maj IS

--declare components used in architecture
COMPONENT and2 PORT(in1, in2 : IN BIT; out1 : OUT BIT);
END COMPONE