VHDL语言的设计方法

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY half_adder IS
PORT(a : IN std_logic;
b : IN std_logic;
s : OUT std_logic; --sum
co : OUT std_logic); --carry out
END half_adder;
ARCHITECTURE half_adder OF half_adder IS
SIGNAL c,d:std_logic;
BEGIN
co<=a AND b; s<=a XOR b;
--logic relation due to truth table

END half_adder;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY full_adder IS
PORT(a,b,cin : IN std_logic;
--cin represents carry in from low bit
co,s : OUT std_logic);
END full_adder;
ARCHITECTURE full_adder OF full_adder IS
COMPONENT half_adder
--component declaration of half adder
PORT(a,b : IN std_logic;
s,co : OUT std_logic);
END COMPONENT ;
SIGNAL u0_co,u0_s,u1_co:std_logic;
--define two signals，represent component inner connection
BEGIN
--connection of h