怎样用VHDL设计一位的BCD码加法器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity eda is
port(
clk:in std_logic;
q:buffer std_logic_vector(3 downto 0);
reset:in std_logic);
end eda;
architecture art of eda is
begin
process(clk,reset,q)
begin
if reset='1' then
q<="0000";
elsif clk'event and clk='1' then
q<=q+1;
end if ;
end process;
end art;

楼上的没有输出怎么验证啊！